Zilog Z16C35 Manuale Utente Pagina 188
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Application Note
The Z180™ Interfaced with the SCC at MHZ
7
Write Cycle Timing
Figure 11 illustrates the SCC Write cycle timing. All
register addresses and /INTACK are stable throughout the
cycle. The timing specification of the SCC requires that the
/CE signal (and address) be stable when /RD is active.
Data is available to the SCC before the falling edge of /WR
and remains active until /WR goes inactive.
Figure 10. SCC Read Cycle Timing
Address
/INTACK
/CE
/RD
D7-D0
Data Valid
Address Valid
Figure 11. SCC Write Cycle Timing
Address
/INTACK
/CE
/WR
D7-D0
Data Valid
Address Valid
Page 182 of 316
UM011002-0808
- User Manual 1
- Revision History 3
- Table of Contents 4
- 1.1 INTRODUCTION 7
- Page 2 of 316 8
- Page 3 of 316 9
- 1.3 Pin Description 12
- Page 7 of 316 13
- Page 8 of 316 14
- Page 9 of 316 15
- Page 10 of 316 16
- 2.1 Introduction 17
- Page 12 of 316 18
- 2.2.3 Data Transfers 19
- 2.3.1 Polling 20
- 2.3.2 Interrupts 21
- 2.3.3 DMA Interrupts 22
- 2.4 REGISTER ACCESS 23
- Page 18 of 316 24
- Page 20 of 316 26
- 2.4.4 DMA Cell Registers 28
- Page 23 of 316 29
- Page 25 of 316 31
- Support Circuitry 32
- Page 27 of 316 33
- 3.3 BAUD RATE GENERATOR 34
- Page 29 of 316 35
- Page 30 of 316 36
- 3.4 DATA ENCODING/DECODING 37
- Page 32 of 316 38
- Page 33 of 316 39
- Page 34 of 316 40
- Page 35 of 316 41
- Page 36 of 316 42
- Page 37 of 316 43
- Page 38 of 316 44
- 3.6 CLOCK SELECTION 46
- Page 41 of 316 47
- Page 43 of 316 49
- 3.7 CRYSTAL OSCILLATORS 50
- Page 45 of 316 51
- Page 46 of 316 52
- Page 47 of 316 53
- Page 48 of 316 54
- 4.2 ASYNCHRONOUS MODE 55
- 4.2.1 Asynchronous Transmit 56
- Page 51 of 316 57
- Page 52 of 316 58
- Page 53 of 316 59
- Page 54 of 316 60
- Page 55 of 316 61
- Page 56 of 316 62
- Page 57 of 316 63
- WR4 0,1 select parity 64
- WR5 1 RTS 64
- 2 select CRC generator 64
- Page 59 of 316 65
- Page 60 of 316 66
- Page 61 of 316 67
- Page 62 of 316 68
- Page 63 of 316 69
- Page 64 of 316 70
- Page 65 of 316 71
- Page 67 of 316 73
- Page 68 of 316 74
- Page 69 of 316 75
- 4.4.1 SDLC Transmit 76
- Page 71 of 316 77
- Page 72 of 316 78
- WR4 1-0 Select parity 79
- WR5 2 Select CRC-CCITT 79
- 4.4.2 SDLC Receive 80
- Page 75 of 316 81
- Page 76 of 316 82
- Page 77 of 316 83
- Page 78 of 316 84
- Page 79 of 316 85
- 4.4.3 SDLC LOOP MODE 86
- Page 81 of 316 87
- Page 82 of 316 88
- Page 83 of 316 89
- Page 84 of 316 90
- Page 85 of 316 91
- 5.1 INTRODUCTION 92
- 5.2 REGISTER DESCRIPTIONS 92
- Page 87 of 316 93
- 5.2.3 DMA Registers 94
- 5.4 WRITE REGISTERS 95
- Page 90 of 316 96
- Page 91 of 316 97
- Page 92 of 316 98
- Page 93 of 316 99
- Mode Definition) 100
- Page 96 of 316 102
- Page 97 of 316 103
- Page 98 of 316 104
- Page 99 of 316 105
- Page 100 of 316 106
- Page 101 of 316 107
- Page 102 of 316 108
- Page 103 of 316 109
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- Page 108 of 316 114
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- Page 110 of 316 116
- Page 111 of 316 117
- Page 112 of 316 118
- Page 113 of 316 119
- Constant) 120
- Page 116 of 316 122
- Page 117 of 316 123
- Page 118 of 316 124
- Page 119 of 316 125
- 5.5 READ REGISTERS 126
- Page 121 of 316 127
- Page 122 of 316 128
- 5.5.2 Read Register 1 129
- Page 124 of 316 130
- 5.5.3 Read Register 2 131
- 5.5.4 Read Register 3 132
- 5.5.5 Read Register 8 133
- 5.5.6 Read Register 10 133
- 5.5.7 Read Register 12 134
- 5.5.8 Read Register 13 134
- 5.5.9 Read Register 15 135
- Page 130 of 316 136
- 5.6.2 DMA Status Register 137
- Page 132 of 316 138
- Page 133 of 316 139
- Page 135 of 316 141
- Page 136 of 316 142
- 5.6.7 DMA Enable Register 143
- 5.6.8 DMA Control Register 144
- Page 139 of 316 145
- Page 140 of 316 146
- Page 141 of 316 147
- Page 143 of 316 149
- UM011002-0808 149
- Page 145 of 316 151
- Page 146 of 316 152
- Page 147 of 316 153
- Customer Support 154
- PPLICATION 155
- Write Cycle Timing 157
- INPUT/OUTPUT CYCLES 159
- Z80A CPU to Z8500 Peripherals 159
- INPUT/OUTPUT CYCLES 160
- (Continued) 160
- Z90H CPU TO Z8500 PERIPHERALS 164
- INTERRUPT ACKNOWLEDGE CYCLES 169
- EXTERNAL INTERFACE LOGIC 169
- CPU/Peripheral Same Speed 169
- Z8500/Z8500A Peripherals 171
- Software 176
- Interfacing Z80 177
- INTRODUCTION 178
- INTERFACES 179
- Z180 to Memory Interface 179
- EPROM INTERFACE 181
- '74 '74 184
- Z180 TO I/O INTERFACE 185
- (Continued) 189
- SCC Interrupt Operation 189
- Z180 MPU to SCC Interface 191
- SCC I/O Read/Write Cycle 191
- USING EPLD 196
- Application Note 198
- Page 192 of 316 198
- CONCLUSION 210
- GENERAL DESCRIPTION 211
- GENERAL DESCRIPTION 212
- Processor 212
- Address Map 213
- UM011001-0601 216
- IUSC (Continued) 220
- SERIAL INTERFACING 220
- JUMPER SUMMARY 225
- DMA/EPLD LOGIC 226
- DMA/EPLD LOGIC (Continued) 228
- YNCHRONOUS 231
- OMMUNICATIONS 231
- SYNCHRONOUS MODES 232
- SYSTEM INTERFACE 232
- CONTROL BUS 233
- EPROM CONTROL BUS 233
- RAM CONTROL BUS 233
- ADDRESS/DATA BUS 233
- SYSTEM INTERFACE 234
- INITIALIZATION 235
- INITIALIZATION 236
- APPENDIX 238
- SOFTWARE ROUTINES 238
- RECEIVE ROUTINE 240
- TRANSMIT ROUTINE 241
- RECEIVE INT. SERVICE ROUTINE 242
- SDLC TRANSMIT 245
- SDLC RECEIVE 247
- /W//REQ (In /REQ mode) 249
- ONLY MODE 251
- Master SCC 253
- Slave SCC #1 253
- Slave SCC #2 253
- Slave SCC #n 253
- DATA TRANSFER MODES 256
- SDLC PROTOCOL 257
- TRANSMIT OPERATION 262
- RECEIVE OPERATION 262
- SOFTWARE 265
- RECEIVE OPERATION 267
- ESCC/SCC DIFFERENCES 269
- ESCC SYSTEM BENEFITS 271
- TRANSMIT FIFO INTERRUPT 272
- RECEIVE FIFO INTERRUPT 273
- AUTOMATIC /RTS DEASSERTION 274
- MODIFIED WRITE TIMING 280
- HARDWARE CONFIGURATION 284
- TRANSMITTING A LLAP FRAME 286
- RECEIVING LLAP FRAMES 286
- CONCLUSIONS 287
- APPENDIX A 288
- APPENDIX B 298
- SCILLATOR 301
- Quartz Equivalent Circuit 303
- Symbolic Representation 303
- Load Capacitors 305
- Amplifier Characteristics 305
- Signal Line 308
- Layout Should 308
- Avoid High 308
- Lighted Areas 308
- NTERFACING 311
- CONFIGURING THE BUS 315
- APPLICATIONS EXAMPLES 318
- ONTROLLER 321
- ISCC QUESTIONS AND ANSWERS 322
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