ZiLOG Z16C35 manuali

Zilog Z16C35 Manuale Utente (322 pagine)

Marchio: Zilog | Categoria: Sensori | Dimensione: 3.13 MB |

Inglese

Indice

User Manual

1

Revision History

3

Table of Contents

4

1.1 INTRODUCTION

7

Page 2 of 316

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Page 3 of 316

9

1.3 Pin Description

12

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2.1 Introduction

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Page 12 of 316

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2.2.3 Data Transfers

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2.3.1 Polling

20

2.3.2 Interrupts

21

2.3.3 DMA Interrupts

22

2.4 REGISTER ACCESS

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Page 18 of 316

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2.4.4 DMA Cell Registers

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Support Circuitry

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Page 27 of 316

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3.3 BAUD RATE GENERATOR

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3.4 DATA ENCODING/DECODING

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3.6 CLOCK SELECTION

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3.7 CRYSTAL OSCILLATORS

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4.2 ASYNCHRONOUS MODE

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4.2.1 Asynchronous Transmit

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WR4 0,1 select parity

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WR5 1 RTS

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2 select CRC generator

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4.4.1 SDLC Transmit

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WR4 1-0 Select parity

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WR5 2 Select CRC-CCITT

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4.4.2 SDLC Receive

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4.4.3 SDLC LOOP MODE

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5.1 INTRODUCTION

92

5.2 REGISTER DESCRIPTIONS

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Page 87 of 316

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5.2.3 DMA Registers

94

5.4 WRITE REGISTERS

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Mode Definition)

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Constant)

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5.5 READ REGISTERS

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5.5.2 Read Register 1

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5.5.3 Read Register 2

131

5.5.4 Read Register 3

132

5.5.5 Read Register 8

133

5.5.6 Read Register 10

133

5.5.7 Read Register 12

134

5.5.8 Read Register 13

134

5.5.9 Read Register 15

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5.6.2 DMA Status Register

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5.6.7 DMA Enable Register

143

5.6.8 DMA Control Register

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UM011002-0808

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Customer Support

154

PPLICATION

155

Write Cycle Timing

157

INPUT/OUTPUT CYCLES

159

Z80A CPU to Z8500 Peripherals

159

INPUT/OUTPUT CYCLES

160

(Continued)

160

Z90H CPU TO Z8500 PERIPHERALS

164

INTERRUPT ACKNOWLEDGE CYCLES

169

EXTERNAL INTERFACE LOGIC

169

CPU/Peripheral Same Speed

169

Z8500/Z8500A Peripherals

171

Software

176

Interfacing Z80

177

INTRODUCTION

178

INTERFACES

179

Z180 to Memory Interface

179

EPROM INTERFACE

181

'74 '74

184

Z180 TO I/O INTERFACE

185

(Continued)

189

SCC Interrupt Operation

189

Z180 MPU to SCC Interface

191

SCC I/O Read/Write Cycle

191

USING EPLD

196

Application Note

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Page 192 of 316

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CONCLUSION

210

GENERAL DESCRIPTION

211

GENERAL DESCRIPTION

212

Processor

212

Address Map

213

UM011001-0601

216

IUSC (Continued)

220

SERIAL INTERFACING

220

JUMPER SUMMARY

225

DMA/EPLD LOGIC

226

DMA/EPLD LOGIC (Continued)

228

YNCHRONOUS

231

OMMUNICATIONS

231

SYNCHRONOUS MODES

232

SYSTEM INTERFACE

232

CONTROL BUS

233

EPROM CONTROL BUS

233

RAM CONTROL BUS

233

ADDRESS/DATA BUS

233

SYSTEM INTERFACE

234

INITIALIZATION

235

INITIALIZATION

236

APPENDIX

238

SOFTWARE ROUTINES

238

RECEIVE ROUTINE

240

TRANSMIT ROUTINE

241

RECEIVE INT. SERVICE ROUTINE

242

SDLC TRANSMIT

245

SDLC RECEIVE

247

/W//REQ (In /REQ mode)

249

ONLY MODE

251

Master SCC

253

Slave SCC #1

253

Slave SCC #2

253

Slave SCC #n

253

DATA TRANSFER MODES

256

SDLC PROTOCOL

257

TRANSMIT OPERATION

262

RECEIVE OPERATION

262

SOFTWARE

265

RECEIVE OPERATION

267

ESCC/SCC DIFFERENCES

269

ESCC SYSTEM BENEFITS

271

TRANSMIT FIFO INTERRUPT

272

RECEIVE FIFO INTERRUPT

273

AUTOMATIC /RTS DEASSERTION

274

MODIFIED WRITE TIMING

280

HARDWARE CONFIGURATION

284

TRANSMITTING A LLAP FRAME

286

RECEIVING LLAP FRAMES

286

CONCLUSIONS

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APPENDIX A

288

APPENDIX B

298

SCILLATOR

301

Quartz Equivalent Circuit

303

Symbolic Representation

303

Load Capacitors

305

Amplifier Characteristics

305

Signal Line

308

Layout Should

308

Avoid High

308

Lighted Areas

308

NTERFACING

311

CONFIGURING THE BUS

315

APPLICATIONS EXAMPLES

318

ONTROLLER

321

ISCC QUESTIONS AND ANSWERS

322

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