Zilog Z80180 Manuale Utente Scaricare il pdf (Pagina 316)

Z8018x

Family MPU User Manual

300

UM005003-0703

MMU Common Base

Register:

MMU Bank Base Register

MMU Common/Bank

Register

Operation Mode Control

Register

I/O Control Register:

CBR

BBR

CBAR

OMCR

ICR

38

39

3A

3E

3F

Table 57. Internal I/O Registers (Continued)

Register Mnemonics Address Remarks

R/W R/W R/W

00 00000

CB7 CB6 CB5

0

bit

during RESET

R/W

MMU Common Base Register

R/W R/W

11 110000

bit

during RESET

R/W

MMU Common Area Register

R/W R/W

MMU Bank

CB4 CB3 CB2 CB1 CB0

R/W R/W R/W R/W

R/W

R/W R/W R/W

00 00000

BB7 BB6 BB5

0

bit

d

uring RESET

R/W

MMU Bank Base Register

BB4 BB3 BB2 BB1 BB0

R/W R/W R/W R/W

R/W

CA3 CA2 CA1 CA0 BA3 BA2 BA1 BA0

R/W R/W R/W R/W

R/W

11 111111

bit

during RESET

R/W

M1 Enable

I/O Compatibility

MIE MITE IOC —

W

R/W

——

—

—

M1 Temporary Enable

R/W

00 101111

bit

during RESET

R/W

I/O Address

I/O Stop

IOA7 —

R/W

——

—

—

IOA6 IOSTP

R/W

Area Register

1 2 ... 311 312 313 314 315 316 317 318 319 320 321 ... 325 326

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