Zilog Z16C30 Manuale Utente Scaricare il pdf (Pagina 69)

5-2

Z16C30 USC

USER'S MANUAL

UM97USC0100

ZILOG

5.2 ASYNCHRONOUS MODES (Continued)

Minimum 1 Bit Time

(except for "Shaving")

5 to 8 Data Bits,

Plus Optional Parity Bit

Start

Bit

Start

Bit

Stop

Bit

1/2 Bit Time

Receiver detects

Falling Edge

Receiver validates

Start Bit

All 1 Bit TIme

Receiver Samples Data

(and Parity?) Bits

Receiver checks

Stop Bit

Figure 5-1. Asynchronous Data

May be SYNs, Mark,

Space, or Not Driven

SYN

(16)

SYN

(16)

CRC

ETX

(03)

Data

STX

(02)

STX

(16)

SYN

(16)

Message

Figure 5-2. Character Oriented Synchronous Data

UM009402-0201

1 2 ... 64 65 66 67 68 69 70 71 72 73 74 ... 207 208

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