Zilog EZ80F916 Manuale Utente Scaricare il pdf (Pagina 12)

eZ80F91 Modular Development Kit

User Manual

UM017010-0112 eZ80F91 Module Interface

5 A7 Bidirectional n/a Yes

6 A2 Bidirectional n/a Yes

7 A8 Bidirectional n/a Yes

8 A1 Bidirectional n/a Yes

9 A10 Bidirectional n/a Yes

10 A3 Bidirectional n/a Yes

13 RD Output Low Yes

14 D5 Bidirectional n/a Yes

15 D1 Bidirectional n/a Yes

16 D4 Bidirectional n/a Yes

17 D0 Bidirectional n/a Yes

18 D2 Bidirectional n/a Yes

19 A17 Bidirectional n/a Yes

20 D6 Bidirectional n/a Yes

23 A19 Bidirectional n/a Yes

24 A18 Bidirectional n/a Yes

25 A21 Bidirectional n/a Yes

26 A20 Bidirectional n/a Yes

27 A23 Bidirectional n/a Yes

28 A22 Bidirectional n/a Yes

Table 1. eZ80Acclaim! MDS Adapter Board Peripheral Bus Connector J1

Identification

1,2

(Continued)

Pin Symbol Signal Direction Active Level eZ80F91 Signal Note

Notes:

1. To simplify the interface description, Power and Ground nets are omitted from this table. The entire interface

is represented in the eZ80Acclaim! MDS Adapter Board schematics; see Figures 8 and 9.

2. External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy the

timing requirements for the eZ80 CPU. All unused inputs should be pulled to either V

or GND, depending on

their inactive levels, to reduce power consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK

output can be deactivated via software in the eZ80F91 MCU’s Peripheral Power-Down Register.

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